![modelsim testbench modelsim testbench](https://sudip.sites.olt.ubc.ca/files/2015/09/6-Verilog-code-for-an-8-Bit-Up-Counter-testbench.-940x732.jpg)
As I add more test cases, the run length increases. I set the run length and click the run button.
#MODELSIM TESTBENCH SIMULATOR#
What I'm doing right now, is writing the test cases in the testbench and using wait for clk_period I launch the simulator and I have to specify the run length, which is the number of times I've written the above statement, multiplied by 50ns. Those are good ideas but in this case, I'm testing a combinational circuit, so no clock. Making their reset input active usually fixes the problem. Vendor PLL models can do that, for example.
#MODELSIM TESTBENCH CODE#
I say eventually because there can be other (hidden) events pending, for example if you have some code that's waiting on a signal with a timeout.ĮDIT: this can fail to stop if there are blocks in your design that contain their own oscillators, providing an infinite supply of future events. Making simulation_running false will stop the clocks, and (eventually) stop the simulation. Try adding a (boolean) signal called "simulation_running", and changing the clock generation toĬlk <= not clk after half_period when simulation_running Stopping all your clocks is a way of doing that and is something you can control from inside your testbench. Modelsim will stop the simulation when either (1) it reaches the time you gave it on the command line ( run 20 us) or (2) when there are no more events to process. Is there a way to do something like this but in the testbench itself rather than the command window? Use “run ms” to specify how much time you want to simulate for. It could be the testbench itself that controls how much time passes when simulating, then you’ll only need the “run -all” command
#MODELSIM TESTBENCH MANUAL#
I looked at the reference manual for ModelSIM and found that it uses a RunLength variable for the default run length, stored in the modelsim.ini file so maybe I could specify it there using vhdl but maybe not worth the extra hassle to save a few seconds.īy 'beforehand' I mean before running the simulator, and by 'begins' I mean when the waveform window shows up I want to automate this process and I was hoping there would be a way to do something like constant max_sim_time : integer := 500 and the simulator would just pick that up from the testbench. So I have to repeat the process every time: count how many wait statements I have determine what the run length is type it in run. The time stamps show these as test cases 1 - 4, err_cnt is a variable so it was incremented in the last two.Īnd that prevents the first report here: - summary of all the testsĪs Brian commented the assert true is never false and you won't execute the second report statement in the summary.What I'm doing right now, is writing the test cases in the testbench and using wait for clk_period I launch the simulator and I have to specify the run length, which is the number of times I've written the above statement, multiplied by 50ns. You'd find that test cases 3 and test cases 4 increment err_cnt without note): err_cont = note): err_cont = note): err_cont = note): err_cont = 2 Report "err_cont = " &integer'image(err_cnt) If you sprinkle report statements for err_cnt immediately following the if statements in each test case: if (T_Q/=T_I) then Report "Something wrong, check again pls!" Report "Testbench of register completely successfully!" concurrent process to offer the clock signalĪssert (T_Q="10") report "Test1 Failed!" severity error Īssert (T_Q="10") report "Test2 Failed!" severity error Īssert (T_Q="00") report "Test3 Failed!" severity error Īssert (T_Q="00") report "Test4 Failed!" severity error U_reg: reg port map (T_I, T_clock, T_load, T_clear, T_Q) Signal T_Q: std_logic_vector(1 downto 0) Signal T_I: std_logic_vector(1 downto 0) Port( I: in std_logic_vector(1 downto 0) i am using Modelsim PE student version 10.4a and i am running the simulation for 100 ns. I am writing a code and test bench for 2 bit register, but in my test bench my assert report statement are not showing up in the console, when i run the simulation of the test bench.